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Integrated Circuit Systems, Inc.
ICS9248-98
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 440BX/VIA Apollo 133 style chipset. Output Features: * 2 - CPUs @2.5V, up to 166MHz. * 1 - IOAPIC @ 2.5V * 13 - SDRAM @ 3.3V * 6 - PCI @3.3V, * 1 - 48MHz, @3.3V fixed. * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support power management: PCI, CPU stop and Mode * Spread spectrum for EMI control (0 to -0.5%, 0.25%). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: <250ps * PCI - PCI: <500ps * BUFFER_IN-SDRAM: <5ns * CPU(early)-PCI: Min=1.0ns, Typ=2.3ns, Max=4.0ns
Pin Configuration
VDD1 *PCI_STOP/REF0 GND X1 X2 VDD2 *MODE/PCICLK_F **FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFER IN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1/FS2* GND CPUCLK_F CPUCLK1 VDDL2 CLK_STOP#* SDRAM_F GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0* 24MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND
Block Diagram
PLL2 /2 X1 X2 BUFFER IN XTAL OSC 48MHz 24MHz IOAPIC REF(1:0) CPUCLK_F PLL1 Spread Spectrum FS(3:0) 4 MODE
STOP
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 80.00 75.00 83.31 66.82 103.00 112.01 68.01 100.23 120.00 114.99 109.99 105.00 140.00 150.00 124.00 132.99 PCICLK (MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25
STOP
2
CPUCLK 1
LATCH
STOP
12
SDRAM (11:0) SDRAM_F
4
POR
CLK_STOP# PCI_STOP# SDATA SCLK Control Logic Config. Reg.
PCI CLOCK DIVDER
STOP
5
PCICLK (4:0) PCICLKF
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ICS9248-98
ICS9248-98
Pin Descriptions
PIN NUMBER 1 2 3,9,16,22, 33,39,45 4 5 6,14 7 MODE1, 2 FS3 8 13, 12, 11, 10 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 26 27 40 41 42 43 44 46 47 48 PCICLK0 PCICLK (4:1) BUFFER IN SDRAM (11:0) VDD3 SDATA SCLK 24MHz FS1 FS0
1, 2
PIN NAME VDD1 REF0 PCI_STOP#1 GND X1 X2 VDD2 PCICLK_F
TYPE DESCRIPTION P W R REF, XTAL power supply, nominal 3.3V O U T 14.318 Mhz reference clock. Halts PCICLK clocks at logic 0 level, when input low IN (In mobile mode, MODE=0) PWR IN OUT PWR OUT IN IN OUT OUT IN OUT PWR I/O IN OUT IN OUT IN PWR OUT IN PWR OUT OUT OUT IN OUT PWR Ground Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (36pF) Supply for PCICLK_F and PCICLK, nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CLK_STOP# This asynchronous input halts CPUCLK, IOAPIC & SDRAM clocks at logic "0" level when driven low. Supply for CPU clocks 2.5V nominal CPU clock outputs, powered by VDDL2. Low if CLK_STOP# = Low Free running CPU clock. Not affected by the CLK_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IOAPIC clock output. 14.318 MHz Powered by VDDL1. Supply for IOAPIC, 2.5V nominal
48MHz
1, 2
VDD4 SDRAM_F CLK_STOP# VDDL2 CPUCLK1 CPUCLK_F REF1 FS21, 2 I OA P I C VDDL1
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9248-98
General Description
The ICS9248-98 is a single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2 C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS924898 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD1 = REF, X1, X2 VDD2 = PCICLK_F, PCICLK VDD3 = SDRAM, supply for PLL core VDD4 = 24MHz, 48MHz VDDL1 = IOAPIC VDDL2 = CPUCLK 1, CPUCLK_F
Mode Pin - Power Management Input Control
MODE, Pin 7 (Latched Input) 0 1 Pin 2 PCI_STOP# (Input) REF0 (Output)
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ICS9248-98
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-98
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2, Bit 7:4
Bit 3 Bit 1 Bit 0
Description CPUCLK PCICLK Bit (2, 7, 6, 5, 4) (MHz) (MHz) 0 0 0 0 0 80.00 40.00 0 0 0 0 1 75.00 37.50 0 0 0 1 0 83.31 41.65 0 0 0 1 1 66.82 33.41 0 0 1 0 0 103.00 34.33 0 0 1 0 1 112.01 37.34 0 0 1 1 0 68.01 34.01 0 0 1 1 1 100.23 33.41 0 1 0 0 0 120.00 40.00 0 1 0 0 1 114.99 38.33 0 1 0 1 0 109.99 36.66 0 1 0 1 1 105.00 35.00 0 1 1 0 0 140.00 35.00 0 1 1 0 1 150.00 37.50 0 1 1 1 0 124.00 31.00 0 1 1 1 1 132.99 33.25 1 0 0 0 0 135.00 33.75 1 0 0 0 1 129.99 32.50 1 0 0 1 0 126.00 31.50 1 0 0 1 1 118.00 39.33 1 0 1 0 0 115.98 38.66 1 0 1 0 1 95.00 31.67 1 0 1 1 0 90.00 30.00 1 0 1 1 1 85.01 28.34 1 1 0 0 0 166.00 41.50 1 1 0 0 1 160.01 40.00 1 1 0 1 0 154.99 38.75 1 1 0 1 1 147.95 36.99 1 1 1 0 0 145.98 36.50 1 1 1 0 1 143.98 35.99 1 1 1 1 0 141.99 35.50 1 1 1 1 1 138.01 34.50 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0.25% Center Spread 0 - Running 1- Tristate all outputs
PWD
0,0101 Note1
0 1 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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ICS9248-98
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
40 43 44
PWD
X 1 1 1 1 1 1 1
DESCRIPTION
Latched FS2# (Reserved) (Reserved) (Reserved) SDRAM_F (Reserved) CPUCLK1 CPUCLK_F
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
7 13 12 11 10 8
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) PCICLK_F (Reserved) PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
PIN#
26 25 17, 18, 20, 21 28, 29, 31, 32 34, 35, 37, 38
PWD
1 X 1 1 1 1 1 1
DESCRIPTION
(Reserved) Latched FS0# 48MHz 24 MHz (Reserved) SDRAM (11:8) SDRAM (7:4) SDRAM (3:0)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
1 1 1 1 X 1 X 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved)
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
PIN# PWD
47 46 2 1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) IOAPIC0 (Reserved) (Reserved) REF1 REF0
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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ICS9248-98
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-98. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) IOAPIC
SDRAM CPUCLK CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-98. 3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-98 CLK_STOP# signal. SDRAM's are controlled as shown. 5. All other clocks continue to run undisturbed.
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ICS9248-98
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-98. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-98 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-98 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-98. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9248-98
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS924898 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-98
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions
Operating Voltage, VDD Supply . . . . . . . . . . . 2.5 to 3.7V Operating Voltage, VDDL Supply . . . . . . . . . . 1.8 to 3.7V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD =VDDL= 3.3 V +/-5% (unless otherwise stated) SYMBOL V IH V IL I IH I IL1 I IL2 I Operating Supply Current DD3.3OP66 IDD3.3OP100 Input frequency Fi Input Capacitance1 Clk Stabilization1
1
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current
CONDITIONS
MIN 2 VSS - 0.3 -5 -200
TYP
V IN=V DD V IN = 0 V; Inputs with no pull-up resistors V IN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz V DD = 3.3 V Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
MAX UNITS VDD + 0.3 V 0.8 V 5 uA uA uA 180 16 5 45 3 mA MHz pF pF ms
12 27
94 130 14.318
CIN CINX TSTAB
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5%, VDDL=2.5V +/- 5% (unless otherwise stated) SYMBOL CONDITIONS I DD2.5OP66 CL = 0 pF; Select @ 66.8 MHz Operating Supply Current I DD2.5OP100 CL = 0 pF; Select @ 100 MHz 1 Skew TCPU-PCI VT =1.5 V; VTL = 1.25V
1
PARAMETER
MIN
TYP 12 9 2.46
MAX 72 100 4
UNITS mA ns
1
Guaranteed by design, not 100% tested in production.
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ICS9248-98
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%, VDDL=2.5V +/- 5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL VOH2B VOL2B I OH2B I OL2B t r2B t f2B
CONDITIONS I OH = -8 mA I OL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, V OH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
TYP 2.4 0.17 -58 46 1.08 0.96
MAX UNITS V 0.4 V -16 mA mA 1.6 1.6 55 175 250 ns ns % ps ps
dt2B Duty Cycle 1 Skew window t sk2B Jitter, Cycle-to-cycle1 t jcyc-cyc2B
1
45
49.4 62 216
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Skew window1 Jitter, Absolute1
1 1
SYMBOL VOH1 VOL1 IOH1 I OL1 tr1 tf1 dt1 tsk1 tjabs1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
41
TYP 3.15 0.13 -97 69 1.42 1.35 51 251 180
MAX UNITS V 0.4 V -40 mA mA 2.0 2.0 55 500 500 ns ns % ps ps
45 -500
Guaranteed by design, not 100% tested in production.
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ICS9248-98
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1
SYMBOL VOH3 VOL3 I OH3 I OL3 t r3 t f3 dt3 t sk3 Tprop
CONDITIONS I OH = -28 mA I OL = 20 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
41
TYP 3 0.18 -110 86 1.13 1.11 53.1 215 3.26
MAX UNITS V 0.4 V -40 mA mA 2 2 55 250 5 ns ns % ps ns
Duty Cycle1 Skew window1 Propagation Time1
(Buffer In to Output) 1
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; V DD=3.3V +/- 5%, VDDL=2.5V +/- 5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Jitter, Absolute1
1 1
SYMBOL V OH4B V OL4B I OH4B I OL4B t r4B t f4B dt4B t jabs4B
CONDITIONS I OH = -8 mA I OL = 12 mA V OH = 1.7 V V OL = 0.7 V V OL = 0.4 V, V OH = 2.0 V V OH = 2.0 V, VOL = 0.4 V V T = 1.25 V V T = 1.25 V
MIN 2
19
TYP 2.4 0.17 -58 46 1.14 1.07
MAX UNITS V 0.4 V -16 mA mA 2 2 55 1 ns ns % ps
45 -1
52.7 0.27
Guaranteed by design, not 100% tested in production.
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ICS9248-98
Electrical Characteristics - REF, 48MHz, 24MHz
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1
SYMBOL VOH5 VOL5 I OH5 I OL5 t r5 t f5 dt5 t jabs5
CONDITIONS I OH = -12 mA I OL = 10 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 3.03 0.23 -50 40 1.26 1.57 53.3
MAX UNITS V 0.4 V -22 mA mA 4.0 4.0 55 1 ns ns % ns
Duty Cycle1 Jitter, Absolute1
1
45 -1
Guaranteed by design, not 100% tested in production.
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ICS9248-98
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
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ICS9248-98
SYMBOL
N
c
In Millimeters COMMON DIMENSIONS MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MAX .095 .008 .008 .110 .016 .0135
A
L
A1 b c D E E1 e
INDEX AREA
E1
E
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
12 D h x 45
h
L N VARIATIONS N
A A1
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MAX 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MAX .380 .455 .630 .730 .830
6/ 1/ 00 REV B
-Ce
b SEATING PLANE .10 (.004) C
28 34 48 56 64
JEDEC MO- 118 DOC# 10- 0034
Ordering Information
ICS9248yF-98LF-T
Example:
ICS XXXX y F PPP LF- T
Designation for tape and reel packaging Lead Free (Optional) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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